Effect of fission products on tensile strength of UO<sub>2</sub> Σ3 (111)/[1<math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si1.svg" class="math"><mover accent="true"><mn>1</mn><mo stretchy="true">¯</mo></mover></math>0] and UO<sub>2</sub> Σ11 (1<math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si1.svg" class="math"><mover accent="true"><mn>1</mn><mo stretchy="true">¯</mo></mover></math>3)/[110] grain boundaries from first-principles study

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How often does the "slow path" actually trigger? With 32 TLB entries covering 128 KB, Intel claimed a 98% hit rate for typical workloads of the era. That sounds impressive, but a 2% miss rate means a page walk every 50 memory accesses -- still quite frequent. So the 386 overlaps page walks with normal instruction execution wherever possible. A dedicated hardware state machine performs each walk:

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